Display Controllers
Digital Blocks’ Display Controller Verilog IP Cores support a wide range of LCD/OLED display resolutions, with the standard release providing resolutions from 320×240 up to 1920×1080 Full HD. Advanced releases add capabilities for 4K and 8K display panels.
Releases contain a variety of optional features from basic baseline display requirements up to advanced display processing features such multi-layer overlay window composition with Alpha Blending, Scaling, Color Space Conversion, 4:2:0 and 4:2:2 YCrCb up-sampling, as well as Frame Buffer Compression and Hardware Cursor.
Optional features provide the customer with targeted features while saving on VLSI resources and licensing costs. Linux OS driver available with support.
Display Controllers | |
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DB9000AX14 | Display Controller – LCD / OLED Panels (AXI4 Bus) |
DB9000AXI3 | Display Controller – LCD / OLED Panels (AXI Bus) |
DB9000AHB | Display Controller – LCD / OLED Panels (AHB Bus) |
DB9000AHB-Lite | Display Controller – LCD / OLED Panels (AHB-Lite Bus) |
DB9000AVLN | Display Controller – LCD / OLED Panels (Avalon Bus) |
DB9000AXI-UHD | Display Controller – Ultra HD LCD / OLED Panels (AXI4/AXI Bus) |
DB9000AXI-DCI | Display Controller – 4K Digital Cinema LCD Panels (AXI4/AXI Bus) |
DB6845 | Motorola MC6845 Functional Equivalent CRT Controller |
Display Link Layer Interface
Digital Blocks’ Display Link Layer Verilog IP Cores consists of the DB-FPD-LVDS-TX for LVDS Interfaces to 1 and 2 Port LCD Panels, up to Ultra HD Resolutions.
Display Link Layer Interface | |
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DB-FPD-LVDS-TX | FPD LVDS Display Interface, 1 Port / 2 Port LCD Panel |
2D Graphics Hardware Accelerator Engines
Digital Blocks 2D Graphics Hardware Accelerator Verilog IP Cores consists of the DB9200AXI4, DB9200AXI, DB9200AHB, and DB9200AVLN.
2D Graphics Hardware Accelerator Engines | |
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DB9200AXI4 | 2D Graphics Hardware Accelerator (AXI4 Bus) |
DB9200AXI | 2D Graphics Hardware Accelerator (AXI Bus) |
DB9200AHB | 2D Graphics Hardware Accelerator (AHB Bus) |
BitBLT Graphics Hardware Accelerator Engines
Digital Blocks BitBLT Graphics Hardware Accelerator Verilog IP Cores consists of the DB9100AXI4, DB9100AXI, DB9100AHB, and DB9100AVLN.
BitBLT Graphics Hardware AcceleratorEngines | |
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DB9100AXI4 | BitBLT Graphics Hardware Accelerator (AXI4 Bus) |
DB9100AXI | BitBLT Graphics Hardware Accelerator (AXI Bus) |
DB9100AHB | BitBLT Graphics Hardware Accelerator (AHB Bus) |
DB9100AVLN | BitBLT Graphics Hardware Accelerator (Avalon Bus) |
Video Signal & Image Processing
Digital Blocks’ Video Signal Processing series consists of the DB1800 NTSC / PAL/ SECAM Video Sync Separator, DB1810 Color Space Converter, DB1820 4:4:4 Y’CbCr to 4:2:2 Y’CbCr Chroma Resampler, DB1825 combined Color Space Converter & Chroma Resampler, DB1830 BT.656 Encoder, and the DB1892 RGB to CCIR601/656 Encoder.
Video Signal & Image Processing | |
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DB1800 | Standard Definition NTSC/PAL/SECAM Video Sync Separator |
DB1810 | Color Space Converter |
DB1820 | 4:4:4 Y’CbCr to 4:2:2 Y’CbCr Chroma Resampler (ITU-R BT.601) |
DB1825 | Color Space converter & Chroma Resampler- 4:4:4 RGB to 4:2:2 Y’CbCr |
DB1830 | ITU-R BT.656 Encoder |
DB1840 | ITU-R BT.656 Decoder |
DB1845 | ITU-R BT.1120 Decoder – HD 1920x1080p |
DB1892 | RGB to ITU-R 601/656 Encoder |
DB1881 | Camera Interface (AHB Bus) |
Direct Memory Access (DMA) Controller
Digital Blocks’ DMA Controller Verilog IP Core configurations support AMBA AXI4 / AXI3 / AHB5 Interfaces and are optimized for high throughput to/from Memory and Peripheral on both small and large data block transfers.
All Multi-channel DMA Controllers support Descriptor Scatter-Gather List (SGL) data transfers with releases targeting CPU AXI / AHB5 backbone DMA Engines, DMA Engine for PCI Express, as well as Peripheral high/low data-rate transfers.
The AXI DMA Controller IP Core contains companion IP for data transfers to/from AXI4-Stream Interface peripherals — see below the next IP group listing.
Multi-Channel DMA Controller | |
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DB-DMAC-MC-AMBA | DMA Controller, 1-16 DMA Channels, Customized AMBA AXI4 / AXI3 / AHB5 Interfaces |
DB-DMAC-MC-AXI | DMA Controller, 1-16 DMA Channels, AXI4 / AXI3 Master Interfaces |
DB-DMAC-MC-AHB | DMA Controller, 1-16 DMA Channels, AHB5 Master Interface |
DMA – AXI4-Stream / AXI Memory Map Transfers
Digital Blocks DB-DMAC-MC2-DL-MM2S-S2MM and DB-DMAC-MC2-CS-MM2S-S2MM Verilog RTL IP Core are a 2- Channel, Scatter-Gather DMA Controller that transfers data between AXI4 Memory Map and AXI4-Stream Interfaces.
Digital Blocks DB-AXI4-STREAM-TO-AXI4-MM-BRIDGE Verilog IP Core accepts AXI4-Stream data and control input, converts the control TID to a AXI4 Memory Map address, and signals a DMA Controller to read the data by way of a AXI4 Slave Memory Map read channel.
Digital Blocks DB-AXI4-MM-TO-AXI4-STREAM-BRIDGE Verilog IP Core accepts AXI4 Memory Map address, control, and data input, converts the address to an AXI4-Stream TID, and sends the data with TID out on the AXI4-Stream Interface.
Digital Blocks conversion IP Cores work with Digital Blocks DMA Controller (i.e. the DB-DMAC-MC-AXI Verilog RTL IP Core) to transfer data to/from AXI4-Stream Interface peripheral to either memory or another peripheral.
AXI4-Stream to/from AXI Memory Map – 2 DMA Channels | |
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DB-DMAC-MC2-DL-MM2S-S2MM | Control by SGL Descriptors |
DB-DMAC-MC2-CS-MM2S-S2MM | Control by SGL Commands Streams |
AXI4-Stream to/from AXI Memory Map – Works with DB-DMAC-MC-AXI | |
DB-AXI4-STREAM-TO-AXI4-MM-BRIDGE | AXI4-Stream Conversion to AXI Memory Map, 16 Channels |
DB-AXI4-MM-TO-AXI4-STREAM-BRIDGE | AXI Memory Map Conversion to AXI4-Stream, 16 Channels |
Low-Latency, High-Speed Networking
Digital Blocks DB-UDP-IP ultra-low latency IP/UDP Protocol Hardware Stack Verilog IP Core targets leading-edge network adapter cards with one or more GbE network links to implement low latency network access.
The DB-RTP-UDP-IP-AV adds RTP hardware processing to 10/100/1000 MbE or 10/40/100 GbE network links and targets Audio/Video Packet Processing such as a IP/UDP/RTP interface to H.264/H.265 CODECs. Both IP Cores contain MAC Layer Pre- & Post-Processing and an ARP Packet Processing for a FPGA or ASIC networking adapter card solution.
Low-Latency, High-Speed Networking – Protocol Stacks | |
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DB-UDP-IP-1GbE | UDP/IP – 1 GbE Protocol Hardware Stack |
DB-UDP-IP-10GbE | UDP/IP – 10 GbE Protocol Hardware Stack |
DB-UDP-IP-25GbE | UDP/IP – 25 GbE Protocol Hardware Stack |
DB-UDP-IP-40GbE | UDP/IP – 40 GbE Protocol Hardware Stack |
DB-UDP-IP-50GbE | UDP/IP – 50 GbE Protocol Hardware Stack |
DB-UDP-IP-100GbE | UDP/IP – 100 GbE Protocol Hardware Stack |
DB-RTP-UDP-IP-AV | RTP/UDP/IP Protocol Hardware Stack – Audio/Video Packet Processing |
DB-RTP-UDP-IP-MPEG-TS | MPEG Transport Stream with RTP/UDP/IP Protocol Hardware Stack – Audio/Video Packet Processing |
MIPI I3C Master/Slave – Inter-Integrated Circuit Controller
Digital Blocks MIPI I3C Master/Slave Controller Verilog IP Cores consists of the DB-I3C-MS-APB, DB-I3C-MS-AHB, DB-I3C-MS-AXI for the AMBA Bus. The I3C Controllers are offered with parameterized FIFOs and Finite State Machine control for off-loading the I3C Controller Master & Slave functions from the processor. The I3C Controllers Master function supports communications with I2C Slave Controllers
Digital Blocks I3C Master-only Controller Verilog IP Cores consists of the DB-I3C-M-APB, DB-I3C-M-AHB, DB-I3C-M-AXI for the AMBA Bus. The I3C Master Controllers are offered with parameterized FIFOs and Finite State Machine control for off-loading the I3C Controller function from the processor. The I3C Master-only version offers a smaller VLSI footprint. The I3C Master-only Controllers support communications with I2C Slave Controllers.
Digital Blocks I3C Slave-only Controller Verilog IP Core consists of the DB-I2C-S-APB, which interfaces via a FIFO to a local host processor, and DB-I2C-S-SCL-CLK-REG & DB-I2C-S-REG, which interfaces to user Registers and/or Memory, without the need for a host processor.
MIPI I3C Master/Slave – Improved Inter Integrated Circuit Controller | |
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DB-I3C-BASIC-MS-APB | I3C Controller IP – Master / Slave, Parameterized FIFO, APB Bus. I3C Basic Specification Design |
DB-I3C-MS-APB | I3C Controller IP – Master / Slave, Parameterized FIFO, APB Bus |
DB-I3C-M-APB | I3C Controller IP – Master, Parameterized FIFO, APB Bus |
DB-I3C-S-APB | I3C Controller IP- Slave, Parameterized FIFO, APB Bus |
DB-I3C-S-SCL-CLK-REG | I3C Controller IP – I3C / I2C Slave, SCL Clock only, Configure User Registers, no CPU Host Required |
DB-I3C-S-REG | I3C Controller IP – I3C / I2C Slave, Configure User Registers, no CPU Host Required |
I2C Master/Slave – Inter-Integrated Circuit Controller
Digital Blocks I2C Master/Slave Controller Verilog IP Cores consists of the DB-I2C-MS-APB, DB-I2C-MS-AHB, DB-I2C-MS-AXI, DB-I2C-M-Hs-Mode for the AMBA Bus and the DB-I2C-MS-AVLN for the Avalon Bus. The I2C Controllers are offered with parameterized FIFOs and Finite State Machine control for off-loading the I2C Controller Master & Slave functions from the processor.
Digital Blocks I2C Master-only Controller Verilog IP Cores consists of the DB-I2C-M-APB, DB-I2C-M-AHB, DB-I2C-M-AXI, DB-I2C-M-Hs-Mode for the AMBA Bus and the DB-I2C-M-AVLN for the Avalon Bus. The I2C Controllers are offered with parameterized FIFOs and Finite State Machine control for off-loading the I2C Controller function from the processor. The I2C Master-only version offers a smaller VLSI footprint.
Digital Blocks I2C Slave-only Controller Verilog IP Core consists of the DB-I2C-S and DB-I2C-S-SCL-CLK and DB-I2C-S-Hs-Mode, which interfaces an I2C Bus to internal user Registers or Memory (SDRAM / SRAM / Flash / FIFO) or any Peripheral or CPU directly connected to an internal AXI / AHB / APB / Avalon Bus. The I2C Slave-only version offers a smaller VLSI footprint.
All Digital Blocks I2C Controllers optionally support SMBus timing & protocol and HID-I2C (Human Interface Device over I2C Protocol Specification). I2C Slave Controllers work with MIPI I3C Master Controllers. Contact Digital Blocks for more information.
I2C Master/Slave – Inter-Integrated Circuit Controller | |
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DB-I2C-MS-AVLN | I2C Controller IP- Master / Slave, Parameterized FIFO, Avalon Bus |
DB-I2C-MS-APB | I2C Controller IP- Master / Slave, Parameterized FIFO, APB Bus |
DB-I2C-MS-AHB | I2C Controller IP- Master / Slave, Parameterized FIFO, AHB Bus |
DB-I2C-MS-AXI | I2C Controller IP- Master / Slave, Parameterized FIFO, AXI Bus |
DB-I2C-MS-Hs-Mode | I2C Controller IP – Master / Slave, Parameterized FIFO, Hs-Mode (3.4 Mbps) AXI/AHB/APB/Avalon Buses |
DB-I2C-MS-SMBUS-AMBA | I2C/SMBus Controller IP – Master / Slave, Parameterized FIFO, AXI/AHB/APB/Avalon Buses, SMBus Protocol |
I2C Master – Inter-Integrated Circuit Controller | |
DB-I2C-M-AVLN | I2C Controller IP – Master, Parameterized FIFO, Avalon Bus |
DB-I2C-M-APB | I2C Controller IP – Master, Parameterized FIFO, APB Bus |
DB-I2C-M-AHB | I2C Controller IP – Master, Parameterized FIFO, AHB Bus |
DB-I2C-M-AXI | I2C Controller IP – Master, Parameterized FIFO, AXI Bus |
DB-I2C-M-Hs-Mode | I2C Controller IP – Master, Parameterized FIFO, Hs-Mode (3.4 Mbps) AXI/AHB/APB/Avalon Buses |
I2C Slave – Inter-Integrated Circuit Controller | |
DB-I2C-S-AVLN | I2C Controller IP – Slave, Parameterized FIFO, Avalon Bus |
DB-I2C-S-APB | I2C Controller IP – Slave, Parameterized FIFO, APB Bus |
DB-I2C-S-AHB | I2C Controller IP – Slave, Parameterized FIFO, AHB Bus |
DB-I2C-S-AXI | I2C Controller IP – Slave, Parameterized FIFO, AXI Bus |
DB-I2C-S-Hs-Mode | I2C Controller IP – Slave, Parameterized FIFO, Hs-Mode (3.4 Mbps) AXI/AHB/APB/Avalon Buses or direct to/from Registers or Memory |
DB-I2C-S-REG | I2C Controller IP – Slave, User Register Interface, No CPU Required |
DB-I2C-S-SCL-CLK | I2C Controller IP – Slave, SCL Clock only, principally for configuring registers in mixed-signal ICs with low noise or low power requirements |
DB-I2C-S-SCL-CLK-APB | I2C Controller IP – Slave, SCL Clock, Parameterized FIFO, APB Bus. For low power requirements in I2C Slave Controller interface to CPU. |
I2C Slave with AMBA Master Bridge – Inter-Integrated Circuit Controller | |
DB-I2C-S-APB-BRIDGE | I2C Controller IP – Slave, Parameterized FIFO, APB Master Interface (I2C2APB) |
DB-I2C-S-AXI-BRIDGE | I2C Controller IP – Slave, Parameterized FIFO, AXI Master Interface (I2C2AXI) |
DB-I2C-S-AHB-BRIDGE | I2C Controller IP – Slave, Parameterized FIFO, AHB Master Interface (I2C2AHB) |
SPI & eSPI Master/Slave – Serial Peripheral Interface Controller
Digital Blocks’ SPI & eSPI Master/Slave Controller Verilog IP Cores consists of the DB-SPI-MS-APB, DB-SPI-MS-AHB, DB-SPI-MS-AXI for the AMBA Bus and the DB-SPI-MS-AVLN for the Avalon Bus. Digital Blocks also offers a Master-only SPI Controller for AMBA Bus. The SPI Controllers are offered with parameterized FIFOs and Finite State Machine control for off-loading the SPI Controller Master & Slave functions from the processor.
The DB-SPI-XIP-FLASH-AMBA is an Octal/Quad/Dual/Single SPI Flash Memory Controller IP providing CPU Programmable IO and optional Boot & Execute-In-Place (XIP) functions via a second AMBA Slave Interface.
The DB-eSPI-SPI-MS-AMBA adds support for the Enhanced SPI Specification.
SPI Execute-In-Place (XIP) Flash Memory Controller | |
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DB-SPI-XIP-FLASH-AMBA | SPI XIP Flash Memory Controller IP – Programmable IO & Execute-In-Place (XIP) via second AMBA Interface |
eSPI Master/Slave – Serial Peripheral Interface Controller | |
DB-eSPI-SPI-MS-AMBA | Enhanced SPI Controller IP- Master/Slave, Parameterized FIFO, AMBA APB / AHB / AXI Bus. Supports eSPI Master & Slave and SPI Master & Slave functions. |
SPI Master/Slave – Serial Peripheral Interface Controller | |
DB-SPI-MS-AMBA | SPI Controller IP- Master/Slave, Parameterized FIFO, AMBA APB / AHB / AXI Bus |
DB-SPI-M-AMBA | SPI Controller IP- Master-only, Parameterized FIFO, AMBA APB / AHB / AXI Bus |
DB-SPI-S-AMBA | SPI Controller IP- Slave-only, Parameterized FIFO, AMBA APB / AHB / AXI Bus |
DB-SPI-MS-AVLN | SPI Controller IP- Master/ Slave, Parameterized FIFO, Avalon Bus |
SPI Slave Bridge – SPI2APB, SPI2AXI, SPIAHB5 | |
DB-SPI-S-AMBA-BRIDGE | SPI Slave IP transfers to/from a AMBA APB, AXI, or AHB Interconnect |
Industry Standard Architecture Peripheral Controllers
Digital Blocks’ Programmable Interrupt Controller (PIC) Verilog & VHDL IP Cores consists of the DB8259A (no clock matching the original i8259A device) and DB8259S (enhanced by Digital Blocks with an all clock design) interrupt controllers. The DB8259A is a full functional equivalent to the i8259A and matches on a per cycle basis while the DB8259S just adds a clock cycle delay to the interrupt output, but the design is streamlined for modern ASIC / ASSP tool flows.
Digital Blocks’ Programmable Peripheral Interface VHDL IP Core consist of the DB8255A, providing 24 lines of programmable I/O. The DB8255A is a full functional equivalent to the i8255A and matches on a per cycle basis.
Digital Blocks’ Programmable Keyboard / Display Interface VHDL IP Core consist of the DB8279, simultaneously and independently interfacing a keyboard and display to a microprocessor. The DB8279 is a full functional equivalent to the i8279 and matches on a per clock cycle basis.
Digital Blocks offers the DB8255, DB8259, and DB8279 part of its 82xx Peripherals Replacement Program in CPLDs & FPGAs.
Programmable Interrupt Controllers | |
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DB8259A | Intel 8259A Functional Equivalent Programmable Interrupt Controller |
DB8259S | Intel 8259A Functional Equivalent Programmable Interrupt Controller |
Programmable Peripheral Interface | |
DB8255A | Intel 8255A Functional Equivalent Programmable Peripheral Interface |
Programmable Keyboard/Display Inteface | |
DB8279 | Intel 8279 Functional Equivalent Programmable Keyboard/Display Interface |