IP Core Evaluation

Evaluation of Digital Blocks IP Cores

Prospective customers can evaluate Digital Blocks’ IP Cores as follows:

• If you would like to Simulate and or Lint, CDC, Synthesize the Verilog/VHDL model, Digital Blocks can assist you in a variety of ways. Please contact Digital Blocks for more details.
• If you would like to test the model in hardware, Digital Blocks can provide a time-limited FPGA programming model. The programming model will contain the IP Core’s full functionality, but will stop after a pre-determined amount of time. Digital Blocks supports Actel, Altera, Atmel, Lattice, Xilinx, and Quicklogic CPLD/FPGA technologies.
• For Altera Quartus II users, Digital Blocks is a member of the Altera OpenCore Plus program. Digital Blocks can provide an encrypted design file of the IP Core along with a license file enabling prospective customers to analyze the IP Core’s performance, functionality, and resource utilization, and place in an Altera CPLD/FPGA for hardware evaluation.

To obtain additional information about evaluatiing Digital Blocks’ IP Cores, please contact us by way of the Contact Us page.