AXI SG DMA Controller – AXI4 / AXI3 Interconnect
The AXI Scatter Gather DMA Controller with Master AXI Interconnect (verilog IP core DB-DMAC-MC-AXI) offers configurable 1 to 256 Channels or releases with lower licensing cost fixed 1-16 Channels, with a per channel CPU Scatter Gather descriptor-driven interface controlling the data transfer between memory subsystems or between memory and a peripheral.
The DB-DMAC-MC-AXI excels at high data throughput on both small and large data sets. Scatter Gather lists transfer data via the AMBA AHB Interconnect between Memory-to-Memory, Peripheral-to/from-Memory, and Peripheral-to-Peripheral.
The AXI DMA Controller features Scatter-Gather capability, with per channel Finite State Control and single- or dual-clock FIFOs (parameterized in depth and width), interrupt controller, and optional data parity generator & checker. The AXI Master data Interface scales from 32- to 1024-bits, with programmable data bursts of 1, 4, 8, 16 words (with the smallest data transfer supported is 1 byte), and up to 16 outstanding read requests, and for AXI4, the availability of programmable QoS and longer data burst lengths up to 256. The AXI DMA Controller also provides a APB or AXI-lite Slave Interface for CPU access to Control/Status Registers. The DB-DMAC-MC-AXI is tuned as a high-performance DMA Engine, for large and small data block transfers.
AXI Scatter-Gather DMA Controller Engines
Digital Blocks DMA Controller Verilog IP Cores offer a flexible CPU programming interface and high-performance transfer rates with leading AMBA Interconnects and standard or customized peripheral interfaces. Digital Blocks DMA Controllers are feature-rich with Multi-Channel, Scatter-Gather capability with IP releases targeting CPU AXI/AHB backbone DMA Engines, PCI Express DMA, Network Ethernet DMA, and Peripheral high/low data-rate DMA transfers.