AXI4 SG DMA Controller – AXI4 AMBA Interconnect
The AXI4 Scatter-Gather (SG) Direct Memory Access (DMA) Controller with Master AXI4 Interconnect (verilog IP core DB-DMAC-MC-AXI) offers RTL SystemVerilog configurable 1 to 256 Channels or RTL Verilog releases with lower licensing cost fixed 1-16 Channels, with a per channel CPU Scatter Gather descriptor-driven interface controlling the data transfer between memory subsystems or between memory and a peripheral. Below is a high-level Microarchitecture view of the AXI4 DMA Controller.
The DB-DMAC-MC-AXI excels at high data throughput on both small and large data sets. Scatter Gather lists transfer data via the AMBA AXI4 Interconnect between Memory-to-Memory, Peripheral-to/from-Memory, and Peripheral-to-Peripheral.
The AXI4 DMA Controller features Scatter-Gather capability, with per channel Finite State Control and single- or dual-clock FIFOs (parameterized in depth and width), interrupt controller, and optional data parity or CRC generator & checker. Both AXI4 and AXI3 AMBA interconnects available. The AXI Master data Interface scales from 32- to 1024-bits, with programmable data bursts of 1, 4, 8, 16 words (with the smallest data transfer supported is 1 byte), and up to AXI3 16 outstanding read requests, and for AXI4, the availability of programmable QoS and longer data burst lengths up to 256. The AXI DMA Controller also provides a AMBA Slave Interface of a full AXI4, AXI3, AXI-lite, or APB for CPU access to Control/Status Registers. The DB-DMAC-MC-AXI is tuned as a high-performance DMA Engine, for large and small data block transfers. Below is an example System View of the AXI4 DMA Controller.
Digital Blocks Family of DMA Controller Engines
In addition to the AXI4 Memory-Map DMA Controller IPs, Digital Blocks offers Multi-Channel Scatter-Gather DMA Controllers that transfers data between AXI4 Memory Map and AXI4-Stream Interfaces (both MM2S and S2MM):
And in addition to AXI4 DMA Controllers, Digital Blocks offers AHB Multi-Channel Scatter-Gather DMA Controllers: