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Low-Latency, High-Speed Networking
Digital Blocks low latency IP, UDP, RTP, MPEG-2 TS (Transport Stream) Hardware Protocol Stack Off-load Engine Verilog Cores target network adapter cards with one or more 10/100 MbE or 1/10/40/100 GbE network links.
Digital Blocks Hardware Protocol Stack Verilog Cores target applications requiring much lower latency than a microprocessor running a software protocol stack. Likewise, the Hardware Protocol Stack excels where multiple application data sessions run in parallel with respect to the network, which would certainly overwhelm a microprocessor.
UDP/IP Hard Protocol Stack
Digital Blocks UDP/IP Off-Load Engine (UOE) SoC FPGA/ASIC solutions (Verilog Cores DB-UDP-IP, DB-UDP-IP-TX, & DB-UDP-IP-RX) target Network Servers and the following Financial Services Companies Trading Platforms: Feed-Handlers, FIX Engines, Ticker Plants, Pre-Trade Risk Checking (Sec. reg. 15c 3-5), Order Books, Symbol Filtering, Matching Engines & Trade selection, Algorithmic Trading, Micro-Burst Handling, and Proprietary Platforms.
RTP Audio/Video Network Streaming
Digital Blocks adds RTP protocol hardware processing to our UDP/IP Off-Load Engine (UOE) SoC FPGA/ASIC solutions (Verilog Core DB-RTP-UDP-IP-AV) and targets Audio/Video Packet Processing such as a RTP/UDP/IP interface to H.264/H.265 CODECs. Both IP Cores contain MAC Layer Pre- & Post-Processing and an ARP Packet Processing for a FPGA or ASIC networking adapter card solution.
MPEG TS Audio/Video Network StreamingThe Digital Blocks adds MPEG Transport Stream (TS) protocol hardware processing to our RTP/UDP/IP Off-Load Engine (Verilog Core DB-RTP-UDP-IP-MPEG-TS) and targets MPEG Transport Stream (TS) processing with RTP/UDP/IP Protocol Hardware Stack, MAC Layer Pre- & Post-Processors, and an ARP Packet Processor targeting high packet throughput or low latency of MPEG Transport of Audio/Video Packets over a Internet Protocol (IP) Network.
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