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Embedded Processors Peripherals
Building on our years of experience developing space-borne and mid-range Processors, Digital Blocks offers the 8-bit 8051 Instruction Set Compatible DB8051C Microcontroller Verilog IP Core. We have architected a high performance, low VLSI footprint, 8-bit Micrcontroller targeting ASSP / ASIC / FPGA development teams.
Embedded Processors with Standard or Custom Peripherals
Digital Blocks 8051 CPU Core IP Microcontroller for ASIC / ASSP / FPGA developers is an 8-bit architecture with 255 instructions complaint with the MCS®51 Instruction Set, and targets Embedded Control & Communications applications with efficient program space requirements. Building upon Digital Blocks DB8051C CPU Core -- with its high performance, small VLSI footprint -- the DDB8051C is based on Digital Blocks Instruction Overlap Architecture.
The Digital Blocks DB8051C-SP (Standard Peripherals) Microcontroller Verilog IP Core contains standard 8051 MCU peripherals, including an interrupt controller, UART, two 16-bit timers, and four 8-bit I/O ports.
The Digital Blocks DB8051C-CP (Configurable Peripherals) Microcontroller Verilog IP Core contains peripherals pre-customized according to the user's application requirements. Any combination of 8051 peripherals, including interrupt controller, UART, 16-bit timers, and N-bit I/O ports, along with SPI, I2C, PWM, Keyboard Controller, as well as enhanced interrupt capabilities with up to 64 interrupts, can be incorporated into the IP release.
The Digital Blocks DB8051C-FSM contains Digital Blocks DB8051C CPU IP Core with up to 800 I/O for programmable, complex Finite State Machine control applications.
I2C - Inter-Integrated Circuit Controllers
Digital Blocks' I2C Controller IP Cores offer parameterized FIFOs and Finite State Machine Control to fully off-load the I2C transfer from the processor. The full off-load capabilities target applications with high performance algorithm requirements or minimal software overhead requirements. Digital Blocks' I2C Controllers are available with Master/Slave, Master-only, and Slave-only feature sets, and in AMBA AXI, AHB, APB as well as Avalon / Qsys bus interfaces.
In addition to interfacing the I2C Bus to a processor, the I2C Controller IP Core can also interface a set of FPGA / ASIC internal Registers to the I2C Bus. Likewise, the I2C Controller can interface Memory (SDRAM / SRAM / Flash) external to the FPGA / ASIC to the I2C Bus.
The I2C IP Core family offers Hs-mode protocol and timing and electrical compliance to the Hs-mode I2C specification as a user selectable opton, within the DB-I2C-MS-Hs-Mode release. With the following features, the DB-I2C-MS-Hs-Mode offers the highest system-level I2C performance capability on the market: (1) 3.4 Mbit/s Hs-Mode transfer on the I2C Bus: (2) DB-I2C-MS Controller FIFO to hold blocks of data plus an off-load Finite State Machine to manage the transfers; (3) streamline DMA controller to move data from the DB-I2C-MS Controller to System Memory or Registers.
See the Digital Blocks IP Core page for a full listing of I2C offerings. For information on reference designs, please see the Digital Blocks I2C IP Core Master / Slave Reference Design page.
Digital Blocks' Programmable Keyboard / Display Interface IP Core consists of the DB8279, which simultaneously and independently interfaces a keyboard and display to a microprocessor. The DB8279 is equivalent to the industry standard Intel 8279 / Siemens SAB8279 / NEC UPD8279. Available in VHDL, this IP core comes with a comprehensive test suite, synthesis scripts, data sheet, and user manual. We offers this IP Core as part of its 82xx Peripherals Replacement Program in CPLDs & FPGAs.
Digital Blocks Programmable Interrupt Controller IP Core series consists of the DB8259A and DB8259S interrupt controllers. Both are full-featured equivalents of the industry standard Intel 8259A / Intersil 82C59A / NEC UPD8259 interrupt controllers. Available in VHDL and Verilog, these 8259 IP cores come with a comprehensive test suite, synthesis scripts, data sheet, and user manual. We offers these IP Cores as part of its 82xx Peripherals Replacement Program in CPLDs & FPGAs.
Digital Blocks Programmable Peripheral Interface IP Core consists of the DB8255A, providing 24 lines of programmable I/O. The DB8255A is a full-featured equivalent to the industry standard Intel 8255A / 82C55A and Intersil 82C55A. Available in VHDL, this IP core comes with a comprehensive test suite, synthesis scripts, data sheet, and user manual. We offers this IP Core as part of its 82xx Peripherals Replacement Program in CPLDs & FPGAs.
AMBA Multi-Channel DMA Controller
The Digital Blocks DB-DMAC-MC-AMBA is a Multi-Channel DMA Controller supporting 1 – 32 independent data block / packet / stream transfers. The Direct Memory Access (DMA) Controller IP Core contains 1 - 32 DMA Controller Engines (i.e. DMA Channels), supporting a 1 – 32 interfaces, including AMBA AXI / AHB / APB interconnects. A customized number of DMA Controller Engines and interfaces are available.
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